Split charge storage node outer spacer process

Details Split charge storage node outer spacer process Split charge storage node outer spacer process

2010-12-29

2011-10-18

Menz, Douglas (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000

Reexamination Certificate

active

08039891

ABSTRACT:
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

REFERENCES:
patent: 7368347 (2008-05-01), Joshi et al.
U.S. Office Action dated Jul. 13, 2010 corresponding to U.S. Appl. No. 11/924,169, filed Oct. 25, 2007.

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