Micro-tile memory interfaces

Details Micro-tile memory interfaces Micro-tile memory interfaces

2005-06-30

2011-10-04

Thai, Tuan (Department: 2185)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S004000, C711S100000, C711S103000, C711S104000, C711S105000, C711S108000, C365S230010, C365S230020, C365S230030, C365S230050, C365S049100, C365S189011, C365S189020, C365S189040, C365S189140, C365S189190, C710S036000, C710S037000, C710S038000, C710S039000, C710S040000

Reexamination Certificate

active

08032688

ABSTRACT:
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

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