Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2008-01-30
2011-10-25
Ha, Dac (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
08045670
ABSTRACT:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
REFERENCES:
patent: 4568888 (1986-02-01), Kimura et al.
patent: 5802123 (1998-09-01), Yoshimura et al.
patent: 5878088 (1999-03-01), Knutson et al.
patent: 5943369 (1999-08-01), Knutson et al.
patent: 6809598 (2004-10-01), Staszewski et al.
patent: 6833875 (2004-12-01), Yang et al.
patent: 7046098 (2006-05-01), Staszewski et al.
patent: 7061409 (2006-06-01), Jantti et al.
patent: 7127022 (2006-10-01), Dieguez
patent: 7145399 (2006-12-01), Staszewski et al.
patent: 7183860 (2007-02-01), Staszewski et al.
patent: 7205924 (2007-04-01), Vemulapalli et al.
patent: 7570182 (2009-08-01), Sheba et al.
patent: 7660376 (2010-02-01), Wang
patent: 7680220 (2010-03-01), Wolaver
patent: 2002/0080901 (2002-06-01), Ham, III
patent: 2005/0243163 (2005-11-01), Ozasa et al.
patent: 2006/0038710 (2006-02-01), Staszewski et al.
patent: 2006/0078079 (2006-04-01), Lu
patent: 2006/0165204 (2006-07-01), Shumarayev et al.
patent: 2007/0075785 (2007-04-01), Kossel et al.
patent: 2007/0085622 (2007-04-01), Wallberg et al.
patent: 2007/0085779 (2007-04-01), Smith et al.
patent: 2008/0056426 (2008-03-01), Si et al.
patent: 2008/0192877 (2008-08-01), Eliezer et al.
patent: 2008/0232531 (2008-09-01), Feller
patent: 2008/0317188 (2008-12-01), Staszewski
Khurram Waheed, et al., Injection Spurs Due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation, IEEE International Symposium on Circuits and Systems May 27-30, 2007, pp. 3291-3294.
Robert Bogdan Staszewski, et al., All Digital PLL and Transmitter for Mobile Phones, IEEE Journal of Solid-State Circuits, vol. 40, No. 12, Dec. 2005, pp. 2469-2482.
Socrates D. Vamvakos, et al., Noise Analysis of Time-to-Digital Converter in All-Digital PLLs, IEEE Dallas/CAS Workshop on Design, Application, Integration and Software, Oct. 2006, pp. 87-90.
Robert Bogdan Staszewski, et al., All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS, ISSCC 2005, Session 17, RF Cellular ICs/17.5, Texas Instruments, Dallas, Pgs. Feb. 8, 2005, pp. 3.
Robert Bogdan Staszewski, A First Multigigahertz Digitally Controlled Oscillator for Wireless Applications, IEEE Transactions on Microwave Theory and Techniques, vol. 51, No. 11, Nov. 2003, pp. 2154-2164.
Texas Instruments, Hybrid Stochastic Gradient Based Digital Controlled Oscillator Gain KDCO Estimation IR-2 in U.S. Appl. No. 11/460,221, filed Jul. 26, 2006.
Mahbuba Sheba, Adaptive Spectral Noise Shaping to Improve Time to Digital Converter Quantization Resolution Using Dithering, IR-8 U.S. Appl. No. 11/853,182, filed Oct. 1, 2007.
Mahbuba Sheba, Digital Phase Locked Loop with Dithering, U.S. Appl. No. 12/114,726, filed May 2, 2008.
Robert Bogdan Staszewski, Digital Phase Locked Loop with Integer Channel Mitigation, U.S. Appl. No. 12/024,881, filed Feb. 1, 2008.
Khurram Waheed, Digital Phase Locked Loop with Gear Shifting, U.S. Appl. No. 12/137,332, filed Jun. 11, 2008.
Staszewski Robert Bogdan
Vemulapalli Sudheer K.
Waheed Khurram
Wallberg John L.
Brady III Wade James
Ha Dac
Haider Syed
Neerings Ronald O.
Telecky , Jr. Frederick J.
LandOfFree
Interpolative all-digital phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interpolative all-digital phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interpolative all-digital phase locked loop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4264851