Indexed table circuit having reduced aliasing

Details Indexed table circuit having reduced aliasing Indexed table circuit having reduced aliasing

2008-02-01

2011-12-27

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S239000

Reexamination Certificate

active

08086831

ABSTRACT:
In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

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