Indexed table circuit having reduced aliasing

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S239000

Reexamination Certificate

active

08086831

ABSTRACT:
In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

REFERENCES:
patent: 5623627 (1997-04-01), Witt
patent: 6279105 (2001-08-01), Konigsburg et al.
patent: 6353882 (2002-03-01), Hunt
patent: 6446171 (2002-09-01), Henriksen
patent: 6484256 (2002-11-01), Levitan et al.
patent: 6516409 (2003-02-01), Sato
patent: 6611910 (2003-08-01), Sharangpani et al.
patent: 6823447 (2004-11-01), Hay et al.
patent: 2002/0178349 (2002-11-01), Shibayama et al.
patent: 2002/0199092 (2002-12-01), Henry et al.
patent: 2004/0210749 (2004-10-01), Biles
patent: 2005/0027967 (2005-02-01), Sperber et al.
patent: 2005/0091475 (2005-04-01), Sodami
patent: 2005/0262332 (2005-11-01), Rappoport et al.
patent: 2005/0268076 (2005-12-01), Henry et al.
patent: 2006/0174096 (2006-08-01), Konigsburg et al.
patent: 2006/0221960 (2006-10-01), Borgione
patent: 2006/0236036 (2006-10-01), Gschwind et al.
patent: 2006/0236074 (2006-10-01), Williamson et al.
patent: 2006/0236080 (2006-10-01), Doing et al.
patent: 2007/0033318 (2007-02-01), Gilday et al.
patent: 0462587 (1991-12-01), None
Levitan et al.; “Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cnche”; U.S. Appl. No. 11/837,893, filed Aug. 13, 7007.
Bradford et al.; “Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache”; U.S. Appl. No. 11/561,002, filed Nov. 17, 2006.
Eberly Jr. et al.; “The Correlation Branch Target Address Cache”; IBM TDB, vol. 36, No. 5, pp. 83-86, May 1996.
Eickenmeyer; “Improving Instruction Cache Branch Prediction with Target Addresses”; IBM TDB, vol. 36, No. 7, pp. 497-498, Jul. 1993.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Indexed table circuit having reduced aliasing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Indexed table circuit having reduced aliasing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Indexed table circuit having reduced aliasing will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4264813

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.