Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2008-07-16
2011-12-27
Garbowski, Leigh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S119000, C716S126000, C716S139000, C327S099000
Reexamination Certificate
active
08086989
ABSTRACT:
A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
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Hailu Eskinder
Yasuda Takeo
Garbowski Leigh
International Business Machines - Corporation
Talpis Matthew B.
Yee & Associates P.C.
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