Forming a semiconductor package including a thermal...

Details Forming a semiconductor package including a thermal... Forming a semiconductor package including a thermal...

2007-06-29

2011-10-04

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S704000, C257S705000

Reexamination Certificate

active

08030757

ABSTRACT:
In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.

REFERENCES:
patent: 7081669 (2006-07-01), Fitzgerald et al.
patent: 2003/0007329 (2003-01-01), Hill
patent: 2004/0125563 (2004-07-01), Vrtis
patent: 2004/0200879 (2004-10-01), Lewis et al.
patent: 2005/0006757 (2005-01-01), Rinella et al.
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patent: 2007/0131737 (2007-06-01), Renavikar et al.
patent: 2008/0142954 (2008-06-01), Hu
patent: 2008/0165502 (2008-07-01), Furman et al.
patent: 2009/0302280 (2009-12-01), Simone et al.
U.S. Appl. No. 11/278,337, filed Mar. 31, 2006, entitled “Coated Thermal Interface In Integrated Circuit Die,” by Susheel Jadhav, et al.
U.S. Appl. No. 11/540,027, filed Sep. 29, 2006, entitled “Composite Solder TIM For Electronic Package,” by Thomas Fitzgerald, et al.

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