Semiconductor memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

C714S025000, C714S048000, C714S719000, C714S720000, C714S733000, C365S200000, C365S201000, C365S189150, C365S210100, C365S203000, C365S230030, C365S145000

Reexamination Certificate

active

08051342

ABSTRACT:
A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to the plurality of bit lines; a plurality of sense amplifiers individually connected to the plurality of data bus lines and configured for detecting memory data stored in corresponding memory cells based on values of currents that are generated in the individual data bus lines in accordance with the memory data.

REFERENCES:
patent: 5606527 (1997-02-01), Kwack et al.
patent: 5682389 (1997-10-01), Nizaka
patent: 6480432 (2002-11-01), Nakayama
patent: 6754094 (2004-06-01), McClure
patent: 6781902 (2004-08-01), Oumiya et al.
patent: 7440347 (2008-10-01), Vogelsang
patent: 2003/0107920 (2003-06-01), Roohparvar
patent: 2008/0037336 (2008-02-01), Kouno
patent: 2009/0257293 (2009-10-01), Kouno
patent: 07-192500 (1995-07-01), None
patent: 2000-195300 (2000-07-01), None
patent: 2000-285697 (2000-10-01), None
patent: 2001-243121 (2001-09-01), None

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