Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2010-11-12
2011-10-04
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C327S200000, C327S214000, C327S090000
Reexamination Certificate
active
08030969
ABSTRACT:
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1is L and a second node N2of a second dynamic circuit1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0to D2is selected using selection signals S0to S2, the first node N1is H, so that the electric charge of the second node N2is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3is H and a fourth node N4is L, so that an n-type transistor Tr6of the second dynamic circuit1B is turned OFF, thereby preventing the second node N2from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected. This circuit is used in a predetermined circuit, such as, for example, a forwarding path of a data path, a crossbar bus switch, or an input portion of a reconfigurable processing unit.
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McDermott Will & Emery LLP
Panasonic Corporation
Tan Vibol
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