Multiple multi-threaded processors having an L1 instruction...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

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Details

C718S104000, C711S121000, C711S122000, C711S130000, C711S151000, C711S158000, C712S032000, C712S207000

Reexamination Certificate

active

08087024

ABSTRACT:
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

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