Data processing system and method for efficient...

Details Data processing system and method for efficient... Data processing system and method for efficient...

2008-04-15

2010-06-29

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S133000, C711S141000, C711S145000, C711SE12023, C711SE12034, C711SE12037, C711SE12069

Reexamination Certificate

active

07747826

ABSTRACT:
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

REFERENCES:
patent: 7389388 (2008-06-01), Cantin et al.

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