Semiconductor device fabrication method and semiconductor...

Details Semiconductor device fabrication method and semiconductor... Semiconductor device fabrication method and semiconductor...

2007-12-13

2010-06-08

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S766000, C257SE29117

Reexamination Certificate

active

07732875

ABSTRACT:
A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 μm in length and running along a Si<100> direction.

REFERENCES:
patent: 6271566 (2001-08-01), Tsuchiaki
patent: 7319258 (2008-01-01), Yang et al.
patent: 7339213 (2008-03-01), Maeda et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2004/0075141 (2004-04-01), Maeda et al.
patent: 2006/0246638 (2006-11-01), Asami et al.
patent: 2007/0063306 (2007-03-01), Doyle et al.
patent: 2007/0246781 (2007-10-01), Tsuchiaki
patent: 2008/0093676 (2008-04-01), Shingu et al.
patent: 2009/0302382 (2009-12-01), Adan et al.
Irie et al.; “In-Plane Mobility Anisotropy and Universality Under Uni-Axial Strains in n- and p- MOS Inversion Layers on (100), (110), and (111) Si”, IEDM Technical Digest, pp. 225-228, (2004).
Sung et al.; “High Performance CMOS Bulk Technology Using Direct Silicon Bond (DSB) Mixed Crystal Orientation Substrates”; IEDM Technical Digest, pp. 235-238, (2005).
Tsuchiaki et al.; “Junction Leakage Generation by NiSi Thermal Instability Characterized Using Damage-Free n+/p Silicon Diodes”; Japanese Journal of Applied Physics, vol. 43, No. 8A, pp. 5166-5173, (2004).

Affiliated with

Also associated with

Rating

Semiconductor device fabrication method and semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device fabrication method and semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device fabrication method and semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4249176