Method for designing cell layout of a semiconductor...

Details Method for designing cell layout of a semiconductor... Method for designing cell layout of a semiconductor...

2007-01-19

2010-06-08

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07735040

ABSTRACT:
With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result.The present invention extracts cells of a specific type specified from outside or cells satisfying specific conditions, arranges these specific cells first or limits a layout position by specifying a layout position, then arranges the remaining cells using a general layout algorithm.

REFERENCES:
patent: 2003/0115564 (2003-06-01), Chang et al.
patent: 2000-250964 (2000-09-01), None

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