Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S063000, C365S156000, C257S393000

Reexamination Certificate

active

07738285

ABSTRACT:
In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

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Japanese Office Action issued in Japanese Patent Application No. JP 2002-098553, mailed Sep. 16, 2008.

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