Method and circuit for generating memory clock signal

Details Method and circuit for generating memory clock signal Method and circuit for generating memory clock signal

2008-07-03

2010-06-08

Donovan, Lincoln (Department: 2816)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S141000, C327S161000, C327S291000, C327S299000

Reexamination Certificate

active

07733129

ABSTRACT:
A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.

REFERENCES:
patent: 6550013 (2003-04-01), Gervais et al.
patent: 2004/0236977 (2004-11-01), Kizer et al.
patent: 2007/0030754 (2007-02-01), Gomm
patent: 2008/0115005 (2008-05-01), Kamada
patent: 2008/0238483 (2008-10-01), Tamlyn
patent: 2008122159 (2008-05-01), None

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