Datapipe CPU register array

Details Datapipe CPU register array Datapipe CPU register array

2006-12-20

2010-06-08

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S036000, C710S038000

Reexamination Certificate

active

07734846

ABSTRACT:
A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

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