Methods of forming wiring to transistor and related transistor

Details Methods of forming wiring to transistor and related transistor Methods of forming wiring to transistor and related transistor

2007-02-22

2010-02-23

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S455000, C257SE21627

Reexamination Certificate

active

07666723

ABSTRACT:
Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

REFERENCES:
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Guarini et al., “Electrical Integrity of State-of-the-Art 0.13 μm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEEE Transactions on Circuits and Systems II, vol. 53, Issue 3, Mar. 2006, 3 pages.
Ieong et al., “Transistor scaling with novel materials,” Materialstoday, vol. 9, No. 6, Jun. 2006, pp. 26-31.

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