Method for forming inlaid interconnect

Details Method for forming inlaid interconnect Method for forming inlaid interconnect

2009-12-07

2010-10-19

Chen, Jack (Department: 2893)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S653000, C438S660000, C257SE21585

Reexamination Certificate

active

07816267

ABSTRACT:
After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.

REFERENCES:
patent: 6492266 (2002-12-01), Ngo et al.
patent: 6770560 (2004-08-01), Abe
patent: 7315084 (2008-01-01), Fujii
patent: 2002/0197856 (2002-12-01), Matsuse et al.
patent: 2004/0009654 (2004-01-01), Abe
patent: 2004-047846 (2004-02-01), None

Affiliated with

Also associated with

Rating

Method for forming inlaid interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming inlaid interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming inlaid interconnect will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4228733