Method and apparatus for translating a virtual address to a...

Details Method and apparatus for translating a virtual address to a... Method and apparatus for translating a virtual address to a...

2007-10-31

2010-10-05

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S207000, C711S216000

Reexamination Certificate

active

07809921

ABSTRACT:
A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

REFERENCES:
patent: 2006/0069899 (2006-03-01), Schoinas et al.

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