Clock tree distributing method

Details Clock tree distributing method Clock tree distributing method

2010-02-02

2010-12-28

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S295000, C716S030000

Reexamination Certificate

active

07859309

ABSTRACT:
A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-dimensional interface arrangement to a one-dimensional interface arrangement according to the conversion rate, forming a one-dimensional clock tree according to the one-dimensional interface arrangement, generating the clock tree corresponding to the two-dimensional interface arrangement by converting the one-dimensional clock tree according to the conversion rate.

REFERENCES:
patent: 6429715 (2002-08-01), Bapat et al.
patent: 6698006 (2004-02-01), Srinivasan et al.
patent: 6701506 (2004-03-01), Srinivasan et al.
patent: 2007/0286323 (2007-12-01), Shimobeppu

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