Electrostatic protection device for semiconductor circuit

Details Electrostatic protection device for semiconductor circuit Electrostatic protection device for semiconductor circuit

2006-06-07

2010-10-05

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S365000, C257SE27004, C438S157000

Reexamination Certificate

active

07808046

ABSTRACT:
The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and sources and drains alternately arranged at both sides of the gates in the semiconductor substrate. A well pickup surrounding every set of the transistor fingers and extending between any two set of the fingers is formed. Metal wires are connected to at least two portions of each of the drains and are also connected to an input/output pad to which Electrostatic Discharge (ESD) excessive current is introduced.

REFERENCES:
patent: 2002/0020845 (2002-02-01), Ogura et al.
patent: 1997-0055319 (1997-07-01), None
patent: 1998-0042939 (1998-08-01), None

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