Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2008-03-06
2010-06-08
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S030000, C326S083000
Reexamination Certificate
active
07733118
ABSTRACT:
Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3633120 (1972-01-01), Battjes
patent: 4333058 (1982-06-01), Hoover
patent: 4527079 (1985-07-01), Thompson
patent: 4658156 (1987-04-01), Hashimoto
patent: 4723110 (1988-02-01), Voorman
patent: 4797631 (1989-01-01), Hsu et al.
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5059835 (1991-10-01), Lauffer et al.
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5144167 (1992-09-01), McClintock
patent: RE34808 (1994-12-01), Hsieh
patent: 5420538 (1995-05-01), Brown
patent: 5491455 (1996-02-01), Kuo
patent: 5521530 (1996-05-01), Yao et al.
patent: 5557219 (1996-09-01), Norwood et al.
patent: 5589783 (1996-12-01), McClure
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5742178 (1998-04-01), Jenkins, IV et al.
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 5801548 (1998-09-01), Lee et al.
patent: 5936423 (1999-08-01), Sakuma et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 5942940 (1999-08-01), Dreps et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 5977796 (1999-11-01), Gabara
patent: 6040712 (2000-03-01), Mejia
patent: 6154047 (2000-11-01), Taguchi
patent: 6175952 (2001-01-01), Patel et al.
patent: 6201405 (2001-03-01), Hedberg
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6222388 (2001-04-01), Bridgewater, Jr.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6281715 (2001-08-01), DeClue et al.
patent: 6288581 (2001-09-01), Wong
patent: 6373278 (2002-04-01), Sung et al.
patent: 6377076 (2002-04-01), Gauthier
patent: 6433579 (2002-08-01), Wang et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 6836149 (2004-12-01), Chow
patent: 6854044 (2005-02-01), Venkata et al.
patent: 6940302 (2005-09-01), Shumarayev et al.
patent: 6956407 (2005-10-01), Baig et al.
patent: 6977534 (2005-12-01), Radelinow
patent: 7224180 (2007-05-01), Hargrove et al.
patent: 7365570 (2008-04-01), King
patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2003/0141919 (2003-07-01), Wang et al.
patent: 2004/0140837 (2004-07-01), Venkata et al.
patent: 2004/0207430 (2004-10-01), Jang
patent: 2004/0233704 (2004-11-01), Shizuki
patent: 2004/0263227 (2004-12-01), Baker et al.
patent: 2005/0095988 (2005-05-01), Bereza et al.
patent: 2005/0160327 (2005-07-01), Baig et al.
patent: 2006/0017462 (2006-01-01), Kao
patent: 2006/0290375 (2006-12-01), Kao
patent: 0 757 124 (2001-05-01), None
B. Gilbert, “The Multi-Tahn Principle: A Tutorial Overview,” IEEE Journal of Solid-State Circuits, vol. 33, No. 1, Jan. 1998.
“Block Diagram for NSM LVDS Output Buffer,” “Circuit Trace from National Semiconductor Device,” National Semiconductor Corporation.
K. Farzan, “A CMOS 10-Gb/s Power-Efficient 4-PAM Transmitter,” IEEE Journal of Solid-State Circuits, vol. 39, No. 3, Mar. 2004, pp. 529-532.
“LVDS Owner's Manual; Design Guide,” National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7.
“ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01,” Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
“Optimized Reconfigurable Cell Array (ORCA), OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief,” Lucent Technolgies Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
Patel, R. et al., “A 3.3-V Programmable Logic Device that Addresses Low Power Supply and Interface Trends,”IEEE 1997 Custom Integrated Circuits Conference, May 1997, pp. 539-542.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note,” Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31),” Xilinx Corporation, Oct. 21, 1998, pp. 1-14.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0),” Xilinx Corporation, Oct. 20, 1998, pp. 1-24.
“DY6000 Family, Fast Field Programmable Gate Array, DY6000 Family Datasheet,” Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.
Hollis Timothy
Keeth Brent
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Tan Vibol
Tran Jany
LandOfFree
Devices and methods for driving a signal off an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Devices and methods for driving a signal off an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Devices and methods for driving a signal off an integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4219025