Method of forming a field effect transistor

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S592000, C438S655000, C438S303000

Reexamination Certificate

active

07833892

ABSTRACT:
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

REFERENCES:
patent: 5247197 (1993-09-01), Ema
patent: 5405798 (1995-04-01), Ema
patent: 5472887 (1995-12-01), Hutter et al.
patent: 5495439 (1996-02-01), Morihara
patent: 5527722 (1996-06-01), Hutter et al.
patent: 5581114 (1996-12-01), Bashir et al.
patent: 5777920 (1998-07-01), Ishigaki et al.
patent: 5844276 (1998-12-01), Fulford et al.
patent: 5866934 (1999-02-01), Kadosh et al.
patent: 5888854 (1999-03-01), Morihara
patent: 5939760 (1999-08-01), Batra et al.
patent: 6063681 (2000-05-01), Son
patent: 6180472 (2001-01-01), Akamatsu et al.
patent: 6180477 (2001-01-01), Liao
patent: 6258671 (2001-07-01), Manning
patent: 6306701 (2001-10-01), Yeh
patent: 6312982 (2001-11-01), Takato et al.
patent: 6329251 (2001-12-01), Wu
patent: 6383872 (2002-05-01), Kadosh et al.
patent: 6383877 (2002-05-01), Ahn et al.
patent: 6420250 (2002-07-01), Cho et al.
patent: 6492665 (2002-12-01), Akamatsu et al.
patent: 6501114 (2002-12-01), Cho et al.
patent: 6548339 (2003-04-01), Manning
patent: 6642134 (2003-11-01), Ishida et al.
patent: 6707154 (2004-03-01), Terauchi et al.
patent: 6806190 (2004-10-01), Lin
patent: 6995437 (2006-02-01), Kinoshita et al.
patent: 7211515 (2007-05-01), Lee et al.
patent: 7276433 (2007-10-01), Parekh et al.
patent: 7439138 (2008-10-01), Parekh et al.
patent: 2001/0005630 (2001-06-01), Kim et al.
patent: 2002/0025644 (2002-02-01), Cho et al.
patent: 2002/0068395 (2002-06-01), Tran et al.
patent: 2003/0025163 (2003-02-01), Kwon
patent: 2003/0073277 (2003-04-01), Cho et al.
patent: 2005/0026380 (2005-02-01), Kammler et al.
patent: 2005/0176202 (2005-08-01), Hisamoto et al.
patent: 2006/0121677 (2006-06-01), Parekh et al.
patent: 2006/0264019 (2006-11-01), Parekh et al.
patent: 2007/0032011 (2007-02-01), Parekh et al.
patent: 2007/0141821 (2007-06-01), Parekh et al.
patent: 2007/0298570 (2007-12-01), Parekh et al.
Cataldo, ‘Embedded DRAM gets pure-logic performance’, [online]. Sep. 11, 2000, EETimes, pp. 1-3, [retrieved on Sep. 9, 2004]. Retrieved from the Internet: <URL:http://www.eetimes.com/article/printableArticle.jhtml;jsessionid=IX1AOLUTNJ4PKOSN...>.

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