Method of fabricating chip package structure

Details Method of fabricating chip package structure Method of fabricating chip package structure

2009-04-15

2010-06-22

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000, C257SE21499

Reexamination Certificate

active

07741149

ABSTRACT:
A chip package structure includes a chip, a lead frame, first and second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface, and chip bonding pads disposed on the active surface. The lead frame having an upper surface and a lower surface includes a die pad, leads, and at least a bus bar. The back surface of the chip is adhered to the die pad. The leads surround the die pad. The bus bar is disposed between the die pad and the leads. The first bonding wires are connected to the chip bonding pads and the bus bar. The second bonding wires are connected to the bus bar and the leads. The upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires, and the second bonding wires.

REFERENCES:
patent: 6989294 (2006-01-01), McLellan et al.

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