Method and mechanism for performing timing aware via insertion

Details Method and mechanism for performing timing aware via insertion Method and mechanism for performing timing aware via insertion

2006-11-17

2010-02-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07665052

ABSTRACT:
A method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster, while the path based method has a better insight of the worst slack/slew for the entire design.

REFERENCES:
patent: 5864487 (1999-01-01), Merryman et al.
patent: 7257782 (2007-08-01), Ho et al.
patent: 7290226 (2007-10-01), Correale et al.
patent: 2006/0101367 (2006-05-01), Fujita et al.

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