Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-01-03
2010-02-02
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S165000, C711S118000, C711S206000, C714S006130
Reexamination Certificate
active
07657701
ABSTRACT:
The wear leveling system and method spreads write cycles across a flash chip, thereby reducing repeated usage of the same areas of the flash chip, and facilitating even usage of all of the memory on the flash chip. When a delete operation occurs in the system and method, the deleted cluster is marked as “dirty” in a table, and the sector address of that cluster is calculated and written into a cache memory. When a write operation occurs, the “dirty” cluster is viewed as a used cluster in order to limit the number of writes to any particular cluster. In a write operation, an unused cluster address is retrieved from a table and a sector address is calculated. If the sector address has a good and low age count, then the write operation writes into the cache memory as well. Before the write operation writes into the cache memory, however, the system and method of the present disclosure checks whether the table requires cleaning and memory updating, or whether a switch to a new table is necessary. Once a purge or sync trigger is effectuated, all of the data written into the cache memory is written into the flash memory.
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Andrus Sceales Starke & Sawall LLP
Kim Hong
The General Electric Company
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