Memory array of non-volatile electrically alterable memory...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S208000, C257SE27103, C257SE29304, C257SE29308, C365S185060, C365S185120

Reexamination Certificate

active

07834388

ABSTRACT:
A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

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patent: 6570810 (2003-05-01), Wong
patent: 6914820 (2005-07-01), Wong
patent: 7177188 (2007-02-01), Iwata et al.

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