Semiconductor testing device and method of testing...

Details Semiconductor testing device and method of testing... Semiconductor testing device and method of testing...

2007-08-22

2010-06-08

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S189011, C365S230030

Reexamination Certificate

active

07733721

ABSTRACT:
The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of pass/fail information in the AFM; a compression failure buffer memory storing data compressed; a good block register storing an address number of a good block prepared; and an address generator, wherein when the block to be compressed is a good one, the good block register sends a address number of the good block to the compress failure buffer memory.

REFERENCES:
patent: 6885956 (2005-04-01), Baba
patent: 7240256 (2007-07-01), Yamane
patent: 7395473 (2008-07-01), Cheng et al.
patent: 2010/0008170 (2010-01-01), Sato et al.
patent: 8-273391 (1996-10-01), None
patent: 2004-117055 (2004-04-01), None
patent: 2004-117056 (2004-04-01), None
patent: WO-2008/050527 (2008-05-01), None

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