Double network physical isolation circuit

Details Double network physical isolation circuit Double network physical isolation circuit

Filed on

2008-08-27

Date issued

2010-11-23

Examiner

Rinehart, Mark (Department: 2111)

Patent Class

Electrical computers and digital data processing systems: input/

SubClass

Intrasystem connection

SubSubClass

Bus interface architecture

Other Related Categories

C710S306000

Type

Reexamination Certificate

Status

active

Patent number

07840743

Description

ABSTRACT:
A double network physical isolation circuit includes a north bridge chip, a bus switch circuit, a first memory, and a second memory. The bus switch circuit includes a first and a second bus switch chip. The first and second memories are connected to different networks. The north bridge chip is connected to the first and second memory. When the bus switch circuit receives a high level signal, the first input pin of the first bus switch chip is in electrical communication with the first output pin of the first bus switch chip, and the first memory is activated. The second memory is grounded through the second bus switch chip. When the bus switch circuit receives a low level signal, the second input pin is in electrical communication with the second output pin of the first bus switch chip, and the second memory is activated. The first memory is grounded through the second bus switch chip.

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patent: 7075808 (2006-07-01), Klein
patent: 7093066 (2006-08-01), Klein
patent: 7245606 (2007-07-01), Barre et al.

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