Digital frequency locked delay line

Details Digital frequency locked delay line Digital frequency locked delay line

2004-08-05

2010-02-16

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07664216

ABSTRACT:
A device includes a signal generator having a delay locked circuit for providing a of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.

REFERENCES:
patent: 4890071 (1989-12-01), Curtis
patent: 5252867 (1993-10-01), Sorrells et al.
patent: 5633608 (1997-05-01), Danger
patent: 5764092 (1998-06-01), Wada et al.
patent: 6114890 (2000-09-01), Okajima et al.
patent: 6137325 (2000-10-01), Miller, Jr.
patent: 6160860 (2000-12-01), Larsson
patent: 6242955 (2001-06-01), Shen et al.
patent: 6281726 (2001-08-01), Miller, Jr.
patent: 6490207 (2002-12-01), Manning
patent: 6542040 (2003-04-01), Lesea
patent: 6636093 (2003-10-01), Stubbs et al.
patent: 6727739 (2004-04-01), Stubbs et al.
patent: 6759883 (2004-07-01), Gomm
patent: 6774687 (2004-08-01), Gomm et al.
patent: 6774690 (2004-08-01), Baker et al.
patent: 6777995 (2004-08-01), Harrison
patent: 6781861 (2004-08-01), Gomm et al.
patent: 6791381 (2004-09-01), Stubbs et al.
patent: 6798259 (2004-09-01), Lin
patent: 6803826 (2004-10-01), Gomm et al.
patent: 6809974 (2004-10-01), Jones et al.
patent: 6809990 (2004-10-01), Thomann et al.
patent: 6819151 (2004-11-01), Mikhalev et al.
patent: 6819603 (2004-11-01), Jones et al.
patent: 6839301 (2005-01-01), Lin et al.
patent: 6839860 (2005-01-01), Lin
patent: 6842399 (2005-01-01), Harrison
patent: 6845459 (2005-01-01), Lin
patent: 6850107 (2005-02-01), Gomm
patent: 6868504 (2005-03-01), Lin
patent: 6876239 (2005-04-01), Bell
patent: 6912666 (2005-06-01), Lin
patent: 2002/0006178 (2002-01-01), Takagi et al.
patent: 2002/0053933 (2002-05-01), Takahashi
patent: 2002/0180500 (2002-12-01), Okuda et al.
patent: 2003/0206043 (2003-11-01), Chung
patent: 2003/0215040 (2003-11-01), Bell et al.
patent: 2004/0117683 (2004-06-01), Waller
patent: 2004/0251936 (2004-12-01), Gomm
patent: 2005/0093597 (2005-05-01), Kwak
patent: 2309522 (2000-11-01), None
patent: 315489 (1989-05-01), None
patent: 370170 (1990-05-01), None
patent: 0878910 (1998-11-01), None
patent: 383486 (1997-09-01), None
US 6,249,165, 06/2001, Harrison (withdrawn)
Chung, Ching-Che, et al., “A new DLL-based approach for all-digital multiphase clock generation”,IEEE Journal of Solid-State Circuits, 39(3), (Mar. 2004),469-475.
Efendovich, A , et al., “Multifrequency zero-jitter delay-locked loop”,IEEE Journal of id-State Circuits, 29(1), (Jan. 1994),67-70.
Gothandaraman, A , et al., “An all-digital frequency locked loop (ADFLL) with a pulse output direct digital frequency synthesizer (DDFS) and an adaptive phase estimator”,Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE, (Jun. 8-10, 2003),303-306.
Hamamoto, T , “A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM”,IEEE Journal of Solid-State Circuits, 39(1), (Jan. 2004),194-206.
Ishibashi, K , “A novel clock distribution system for CMOS VLSI”,1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings, (Oct. 3-6, 1993),289-292.
Watanabe, T , et al., “An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time”,IEEE Journal of olid-State Circuits, 38(2), (Feb. 2003),198-204.
“Search Report for International Application No. PCT/US2005/027863”, (Nov. 22, 2005), 4 pgs.
“Taiwanese Application Serial No. 94125401, Office Action mailed Oct. 21, 2009”, 11 pgs.
“Japanese Application Serial No. 2007-525024, Office Action mailed Nov. 10, 2009”, 4 pgs.

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