Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-12-08
2010-11-02
Mandala, Victor A (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S331000, C257SE29257
Reexamination Certificate
active
07825465
ABSTRACT:
A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.
REFERENCES:
patent: 5451800 (1995-09-01), Mohammad
patent: 5534713 (1996-07-01), Ismail et al.
patent: 6020600 (2000-02-01), Miyajima et al.
patent: 6191432 (2001-02-01), Sugiyama et al.
patent: 6200866 (2001-03-01), Ma et al.
patent: 6239463 (2001-05-01), Williams et al.
patent: 6255692 (2001-07-01), Huang
patent: 6350993 (2002-02-01), Chu et al.
patent: 6373112 (2002-04-01), Murthy et al.
patent: 6373122 (2002-04-01), Murthy et al.
patent: 6531748 (2003-03-01), Pfirsch
patent: 6620664 (2003-09-01), Ma et al.
patent: 6700180 (2004-03-01), Huang
patent: 6709912 (2004-03-01), Ang et al.
patent: 6885084 (2005-04-01), Murthy
patent: 6887760 (2005-05-01), Curro et al.
patent: 6902967 (2005-06-01), Beasom
patent: 6943407 (2005-09-01), Ouyang et al.
patent: 7078283 (2006-07-01), Wang
patent: 7078782 (2006-07-01), Shirai et al.
patent: 7238985 (2007-07-01), Jones et al.
patent: 7345342 (2008-03-01), Challa
patent: 7459365 (2008-12-01), Rub et al.
patent: 7504303 (2009-03-01), Yilmaz et al.
patent: 7504691 (2009-03-01), Park et al.
patent: 2005/0199873 (2005-09-01), Tanaka et al.
patent: 2006/0157806 (2006-07-01), Rhodes
patent: 2006/0226455 (2006-10-01), Lee et al.
patent: 2006/0292805 (2006-12-01), Kawamura et al.
patent: 2009/0014814 (2009-01-01), Loechelt et al.
patent: 2009/0114949 (2009-05-01), Hebert
patent: 2006/042040 (2006-04-01), None
patent: 2008/027722 (2008-03-01), None
“The Profiling of Polycrystalline Silicon,” 2 pages, Solecon Labs Technical Note.
Ahoujja et al., “Electrical properties of boron-doped p-SiGeC grown on n—Si substrate,” Applied Physics Letters, 77(9):1327-1329 (Aug. 28, 2000).
Baliga, B. J., Power Semiconductor Devices, 3rd Edition, cover page and pp. 362-367 (1996).
Bouillon et al., “Search for the optimal channel architecture for 0.18/0.12 μm bulk CMOS Experimental study,” IDEM Tech. Digest, 96:559-562 (1996).
Chang et al., “Suppression of boron penetration by polycrystalline Si1-x-yGexCy in metal-oxide-semiconductor structures,” Applied Physics Letters, 74(17):2501-2503 (Apr. 26, 1999).
Chinese Office Action in Related Chinese Application No. 200580034226.2, Mailed Jun. 27, 2008.
Fischetti et al., “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., 80(4):2234-2252 (Aug. 15, 1996).
Huang et al., “Effect of polysilicon depletion on MOSFET I-V characteristics,” Electronics Letters, 29(13):1208-1209 (Jun. 24, 1993).
King et al., “Electrical Properties of Heavily Doped Polycrystalline Silicon-Germanium Films,” IEEE Transactions on Electron Devices, 41(2):228-232 (Feb. 1994).
Lang et al., “Measurement of the band cap of GexSi1-x/Si strained-layer heterostructures,” Appl. Phys. Lett., 47(12):1333-1335 (Dec. 15, 1985).
Langdo et al., “SiGe-free strained Si on insulator by wafer bonding and layer transfer,” Applied Physics Letters, 82(24):4256-4258 (Jun. 16, 2003).
Lee et al., “Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si0.8Ge0.2 Gated PMOS Devices,” IEEE Electron Device Letters, 20(1):9-11 (Jan. 1999).
Leitz et al., “Hole mobility enhancements in strained Si/Si1-yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex (x<y) virtual substrates,” Applied Physics Letters, 79(25):4246-4248 (Dec. 17, 2001).
Li et al., “Carrier velocity-field characteristics and alloy scattering potential in Si1-xGex/Si,” Appl. Phys. Lett., 63(10):1393-1395 (Sep. 6, 2003).
Non Final Office Action for U.S. Appl. No. 11/245,995 Mailed Nov. 30, 2006.
Non-Final Office Action for U.S. Appl. No. 11/469,456, Mailed Mar. 17, 2008.
Notice of Allowance for U.S. Appl. No. 11/469,456, Mailed Oct. 15, 2008.
PCT International Preliminary Report on Patentability for Application No. PCT/US2005/036036, Mailed Apr. 11, 2007.
PCT International Search Report of the International Searching Authority for Application No. PCT/US05/036036, Mailed Jan. 3, 2007.
PCT International Search Report of the International Searching Authority for Application No. PCT/US07/75911, Mailed Feb. 25, 2008.
PCT International Search Report of the International Searching Authority for Application No. PCT/US2008/086081, Mailed Feb. 19, 2009.
PCT Written Opinion of the International Searching Authority for Application No. PCT/US05/036036, Mailed Jan. 1, 2007.
PCT Written Opinion of the International Searching Authority for Application No. PCT/US07/75911, Mailed Feb. 25, 2008.
PCT Written Opinion of the International Searching Authority for Application No. PCT/US2008/086081, Mailed Feb. 19, 2009.
Ricco et al., “Characterization of Polysilicon-Gate Depletion in MOS Structures,” IEEE Electron Device Letters, 17(3):103-105 (Mar. 1996).
Stewart et al., “Suppression of Boron Penetration in P-Channel MOSFETs Using Polycrystalline Si1-x-yGexCy Gate Layers,” IEEE Electron Device Letters, 22(12):574-576 (Dec. 21, 2001).
Sun et al., “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Trans. Electron Devices, vol. ED-27, 12 pages (1980).
Sze, eds., cover page, table of contents and pp. 160-163 from Modern Semiconductor Device Physics, John Wiley & Sons (1998).
Terauchi et al., “Suppression of the Floating-Body Effects in SOI MOSFETs by Bandgap Engineering,” 1995 Symp. VLSI Tech. Digest of Technical Papers, pp. 35-36 (1995).
Van de Walle et al., “Theoretical calculations of heterojunction discontinuities in the Si/Ge system,” Physical Review B, 34(8):5621-5634 (Oct. 15, 1988).
Pan James
Wang Qi
Fairchild Semiconductor Corporation
Mandala Victor A
Townsend and Townsend / and Crew LLP
LandOfFree
Structure and method for forming field effect transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure and method for forming field effect transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for forming field effect transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4184268