Gate patterning of nano-channel devices

Details Gate patterning of nano-channel devices Gate patterning of nano-channel devices

2009-04-03

2010-10-19

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S694000, C438S197000, C257SE21001, C977S938000, C977S762000

Reexamination Certificate

active

07816275

ABSTRACT:
Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

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U.S. Appl. No. 11/760,992, filed Jun. 11, 2007, entitled, “Multi-Layer Mask Method for Patterned Structure Etching,” First Named Inventor: Nicholas Fuller.
U.S. Appl. No. 11/860,459, filed Sep, 24, 2007, entitled, “Methods of Manufacture of Vertical Nanowire FET Devices and FET Devices Produced Thereby,” First Named Inventor: Hariklia Deligianni.

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