Method and structure for low latency load-tagged pointer...

Details Method and structure for low latency load-tagged pointer... Method and structure for low latency load-tagged pointer...

2008-01-31

2010-12-07

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C712S224000

Reexamination Certificate

active

07849293

ABSTRACT:
A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal instruction execution latency. A second higher latency, non-speculative implementation that always produces correct results is invoked by the first when the first guesses incorrectly. The methodologies and structures disclosed herein are intended to be combined with predictive techniques for instruction processing to ultimately improve processing throughput.

REFERENCES:
patent: 4241396 (1980-12-01), Mitchell et al.
patent: 5889986 (1999-03-01), Nguyen et al.
patent: 7003768 (2006-02-01), Daynes et al.

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