Closed loop CESL high performance CMOS device

Details Closed loop CESL high performance CMOS device Closed loop CESL high performance CMOS device

2005-06-29

2010-11-09

Warren, Matthew E (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S649000, C257S900000, C257SE29132, C257SE29162, C257SE29165

Reexamination Certificate

active

07829978

ABSTRACT:
An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.

REFERENCES:
patent: 6764966 (2004-07-01), En et al.
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 2004/0113217 (2004-06-01), Chidambarrao et al.
patent: 2004/0135234 (2004-07-01), Morin et al.
patent: 2004/0235236 (2004-11-01), Hoffmann et al.
patent: 2005/0059228 (2005-03-01), Bu et al.
patent: 2005/0263825 (2005-12-01), Frohberg et al.
patent: 2006/0017098 (2006-01-01), Doczy et al.
patent: 2006/0024879 (2006-02-01), Fu et al.
patent: 2006/0079046 (2006-04-01), Yang et al.
patent: 2006/0157750 (2006-07-01), Kim et al.
patent: 2006/0208250 (2006-09-01), Sun et al.
patent: 2008/0061366 (2008-03-01), Liu et al.
patent: 2008/0258227 (2008-10-01), Wang et al.
Chen, et al., “Extended Scaling of Ultrathin Gate Oxynitride toward Sub-65nm CMOS by Optimization of UV Photo-Oxidation, Soft Plasma/Thermal Nitridation & Stress Enhancement,” 2004 IEEE, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 176-177.
Ghani, T., et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Siicon CMOS Transistors,” 2003 IEEE, IEDM, pp. 978-980.
Iwamoto, T., et al., “A Highly Manfuacturable Low Power and High Speed HfSiO CMOS FET with Dual Poly-Si Gate Electrodes,” 2003 IEEE, IEDM, pp. 639-642.
Kim, Y., et al., “Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer,” 2003 Symposium on VLSI Technology Digests of Technical Papers, pp. 167-168.
Mehrotra, M. et al., “60nm Gate Length Dual-Vt CMOS for High Performance Applications,” 2002 IEEE, 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 124-125.
“Thin Film Hafnium Silicate (HFSiO) Thickness and Composition Measurements by XPS,” HfSiO, Hafnium Silicate High-k Dielectric, Evans Analytical Group Application Note, 2004 Charles Evans & Associates, 2 pages.

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