Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2007-04-16
2010-11-23
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
C712S213000
Reexamination Certificate
active
07840786
ABSTRACT:
A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory.
REFERENCES:
patent: 5761490 (1998-06-01), Hunt
patent: 5887152 (1999-03-01), Tran
patent: 5933850 (1999-08-01), Kumar et al.
patent: 6044455 (2000-03-01), Hara
patent: 6092182 (2000-07-01), Mahalingaiah
patent: 6260134 (2001-07-01), Zuraski, Jr. et al.
patent: 6275927 (2001-08-01), Roberts
patent: 6324621 (2001-11-01), Singh et al.
patent: 6385720 (2002-05-01), Tanaka et al.
patent: 6405303 (2002-06-01), Miller et al.
patent: 6502188 (2002-12-01), Zuraski, Jr. et al.
patent: 6823444 (2004-11-01), Henry et al.
patent: 6854050 (2005-02-01), Zuraski, Jr.
patent: 7024545 (2006-04-01), Zuraski, Jr. et al.
patent: 2005/0268046 (2005-12-01), Heil
Tremaine et al., PINNACLE: IBM MXT in a Memory Controller Chip, Apr. 2001.
Advanced Micro Devices , Inc.
Kindred Alford W
Moll Jesse R
LandOfFree
Techniques for storing instructions and related information... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for storing instructions and related information..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for storing instructions and related information... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4174759