Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-03
2010-06-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07735041
ABSTRACT:
Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.
REFERENCES:
patent: 5764485 (1998-06-01), Lebaschi
patent: 5831867 (1998-11-01), Aji et al.
patent: 5861641 (1999-01-01), Yoeli et al.
patent: 6026224 (2000-02-01), Darden et al.
patent: 6166560 (2000-12-01), Ogura et al.
patent: 6294927 (2001-09-01), Yoeli et al.
patent: 6331790 (2001-12-01), Or-Bach et al.
patent: 6459136 (2002-10-01), Amarilio et al.
patent: 6525350 (2003-02-01), Kinoshita et al.
patent: 6696856 (2004-02-01), Smith et al.
patent: 6750541 (2004-06-01), Ohtsuka et al.
patent: 6873185 (2005-03-01), Cox
patent: 6903390 (2005-06-01), Amarilio et al.
patent: 6924662 (2005-08-01), Amarilio et al.
patent: 7446352 (2008-11-01), Becker et al.
patent: 7511536 (2009-03-01), Amarilio et al.
patent: 2003/0234666 (2003-12-01), Cox
patent: 2004/0027156 (2004-02-01), Amarilio et al.
patent: 2006/0081583 (2006-04-01), Hembree et al.
patent: 2006/0195810 (2006-08-01), Morton
Amarilio Lior
Segal Yoav
Chiang Jack
ChipX, Inc.
Parihar Suchin
Pillsbury Winthrop Shaw & Pittman LLP
LandOfFree
Methods and computer readable media implementing a modified... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and computer readable media implementing a modified..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and computer readable media implementing a modified... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4167694