Computer graphics processing and selective visual display system – Computer graphics display memory system – Register
Reexamination Certificate
2000-07-26
2010-12-07
Hsu, Joni (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Register
C718S107000, C718S102000
Reexamination Certificate
active
07847803
ABSTRACT:
The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a separate program. Instructions from the registers are interleaved in the execution pipeline such that the average latency is one instruction per cycle. This is accomplished even when there is conditional branching and execution latency. When one instruction has a dependency based on execution of a previous instruction, that second instruction is not provided to the execution pipeline until completion of the first instruction. However, in the meantime interleaved instructions from other programs are still being executed while the first instruction of the first program is executing. Thus the pipeline is always full and the processor is always working at peak capacity. The automatic interleaving of instructions permits simplified graphics software routines to be written. There is no need for the programmer or developer to anticipate or attempt to eliminate conditional branching or to worry about instruction latency. The design of the programmable interleaved graphics processing system provides a solution to those problems.
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ATI Technologies ULC
Hsu Joni
Vedder Price P.C.
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