Integrated power supply system analyzing system, integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07669162

ABSTRACT:
Information related to a structure of a multilayer printed circuit board, a physical constant and a mesh is input (Step S701) to generate an equivalent circuit model of the multilayer printed circuit board (Step S702). A transfer matrix is generated with an LSI power source terminal mounting candidate point of the uppermost layer as an input and an LSI power source terminal mounting candidate point of the lowermost layer as an output (Step S703) and the transfer matrix is converted into an impedance matrix (Step S704). Here, a first LSI mounting point is input (Step S705) to select an optimum LSI mounting point (Step S706) and the optimum LSI mounting point and the remaining LSI mounting candidate points are sequentially output (Step S707).

REFERENCES:
patent: 6557154 (2003-04-01), Harada et al.
patent: 6871334 (2005-03-01), Mabuchi et al.
patent: 2003/0109995 (2003-06-01), Mabuchi et al.
patent: 2002-64279 (2002-02-01), None
patent: 2002-064279 (2002-02-01), None
patent: 2002-351937 (2002-06-01), None
patent: 2002-351937 (2002-12-01), None
patent: 2003-6260 (2003-01-01), None
patent: 2003-006260 (2003-01-01), None
Takashi Harada, et al., “Power-Distribution-Plane Analysis for Multilayer Printed Circuit Boards with Spice”, 2000 IEMT/IMC Symposium, Apr. 19-21, pp. 420-425.

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