Memory control apparatus and memory control method

Details Memory control apparatus and memory control method Memory control apparatus and memory control method

2006-12-14

2010-06-15

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C345S501000

Reexamination Certificate

active

07739428

ABSTRACT:
For an electronic apparatus in which data is transferred between a plurality of processing devices and a memory, a technique is provided which prevents the data transfer from being restricted and allows the processing devices to operate efficiently. The order of priorities of data transfer operations through channels is changed on the basis of a relation between thresholds and the amounts of data remaining respectively in FIFO buffers. This prevents the FIFO buffers from becoming empty of data, or from being filled up with data, which allows the devices to operate efficiently.

REFERENCES:
patent: 5241661 (1993-08-01), Concilio et al.
patent: 5793384 (1998-08-01), Okitsu
patent: 2003/0189934 (2003-10-01), Jeffries et al.

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