Method and apparatus for a two-step resist soft bake to...

Details Method and apparatus for a two-step resist soft bake to... Method and apparatus for a two-step resist soft bake to...

2004-01-27

2010-12-07

Toledo, Fernando L (Department: 2895)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

C427S249100

Reexamination Certificate

active

07846851

ABSTRACT:
A semiconductor wafer having no photoresist craters at the completion of a two-step post-apply resist bake (soft bake) in the fabrication of an integrated circuit. A process and method for soft baking the semiconductor wafer so that photoresist layers are free of surface voids or craters. The semiconductor wafer is coated with resist and then baked at both a low-bake temperature and a high-bake temperature. It is theorized that the lower temperature bake either hardens the resist layer before trapped air expands through the resist or displaces the trapped air while the resist layer remains fluid and returns to its conformal shape.

REFERENCES:
patent: 5609995 (1997-03-01), Akram et al.
patent: 6482553 (2002-11-01), Gottert et al.
patent: 7459241 (2008-12-01), Wago
patent: 7534470 (2009-05-01), Madou et al.
Wolf and Tauber; Silicon Processing for the VLSI Era vol. 1: Process Technology; copyright 1986, Lattice Press; Sunset Beach, CA; pp. 429, 434-437, 452 and 453.

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