Host memory interface for a parallel processor

Details Host memory interface for a parallel processor Host memory interface for a parallel processor

2008-09-05

2010-12-07

Rutz, Jared I (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S202000, C712S028000

Reexamination Certificate

active

07849276

ABSTRACT:
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

REFERENCES:
patent: 5446844 (1995-08-01), Steckler et al.
patent: 5953738 (1999-09-01), Rao
patent: 5956274 (1999-09-01), Elliott et al.
patent: 6233646 (2001-05-01), Hahm
patent: 6381671 (2002-04-01), Ayukawa et al.
patent: 6505269 (2003-01-01), Potter
patent: 6519598 (2003-02-01), Nishizawa et al.
patent: 2002/0027824 (2002-03-01), Cowles et al.
patent: 0 584 783 (1993-08-01), None
patent: 01/01242 (2000-06-01), None
Vuillemin, J. et al., “Programmable Active Memories: Reconfigurable Systems Come of Age”, IEEE Transactions on VLSI Systems, vol. 4, No. 1, 1996, pp. 56-69, available from the Internet at http://citeseer.nj.nec.com/vuillemin96programmable.html.

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