Method and apparatus for instruction trace registers

Details Method and apparatus for instruction trace registers Method and apparatus for instruction trace registers

2007-10-25

2010-11-30

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S038110

Reexamination Certificate

active

07844859

ABSTRACT:
A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register.

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Ramer, “Logic Interface to Allow High Performance Event Tracing with Low Performance Monitoring Devices”, IBM Technical Disclosure Bulletin, Oct. 1986, pp. 2076-2079.
Brown et al., “Circuit for Tracing Branch Instructions”, IBM Technical Disclosure bulletin, Dec. 1979, pp. 2651-2654.
Moore, “Instruction Trace Apparatus”, IBM Technical Disclosure Bulletin, Feb. 1978, pp. 3503-3506.
Ryle, “Program Tracing”, IBM Technical Disclosure Bulletin, Dec. 1974, pp. 1865-1866.

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