Reuse of circuit labels for verification of circuit recognition

Details Reuse of circuit labels for verification of circuit recognition Reuse of circuit labels for verification of circuit recognition

2008-02-21

2010-12-28

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07861193

ABSTRACT:
A method for identifying instances of a smaller circuit in a larger circuit is provided. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. The method includes recursively relabeling of each of the plurality of vertices until labels of all neighboring vertices of a selected vertex are zero. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Each successive iteration of the relabeling uses labels of each of the plurality of vertices after a previous iteration of the relabeling. Then, a recursive circuit tracing operation is performed.

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