Method and apparatus to clock-gate a digital integrated...

Details Method and apparatus to clock-gate a digital integrated... Method and apparatus to clock-gate a digital integrated...

2009-01-21

2010-06-29

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S094000, C326S095000

Reexamination Certificate

active

07746116

ABSTRACT:
One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.

REFERENCES:
patent: 6275081 (2001-08-01), Flake
patent: 2004/0225978 (2004-11-01), Fan et al.

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