Semiconductor electrode having improved grain structure and oxid

Details Semiconductor electrode having improved grain structure and oxid Semiconductor electrode having improved grain structure and oxid

1995-05-12

1996-09-17

Tran, Minhloan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, 257321, 257324, H01L 27108, H01L 29788

Patent

active

055571220

ABSTRACT:
The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V.sub.TM) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors.
An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300). The nitrogen doped amorphous silicon oxidizes at a slower rate than undoped amorphous silicon and has less inherent stress resulting in thinner a capacitor dielectric (308) of fewer defects. The capacitor plates (304 and 306) maintain their microcrystalline structure throughout subsequent temperature cycling resulting in increased capacitor area.

REFERENCES:
patent: 4786954 (1988-11-01), Morie et al.
patent: 5289026 (1994-02-01), Ong
Aritome et al., "Reliability Issues of Flash Memory Cells", Proceedings of the IEEE, vol. 81, No. 5, May 1993, pp. 779-781.
Kobayashi et al., "Nitrogen in-situ doped Poly Buffer LOCOS: Simple and Scalable Isolation Technology for Deep-Submicron Silicon Devices", IEEE Technical Digest IEDM, 1994, pp. 683-686.
Muramatsu et al, "The Solution of Over-Erase Problem Controlling Poly-Si Grain Size--Modified Scaling Principles for FLASH Memory", IEEE Technical Digest IEDM, 1994, pp. 847-850.

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