Interconnections for integrated circuits including reducing...

Details Interconnections for integrated circuits including reducing... Interconnections for integrated circuits including reducing...

2008-03-14

2010-11-16

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S675000, C438S687000, C438S691000

Reexamination Certificate

active

07833900

ABSTRACT:
The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.

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patent: 6500754 (2002-12-01), Erb et al.
patent: 7314827 (2008-01-01), Toyoda et al.
patent: 2005/0106848 (2005-05-01), Bailey et al.
E.T. Ogawa et al., Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads, 40th Annual International Reliability Physics Symposium, 2002, 312-321, IEEE 02CH37320, Dallas, Texas.
T. Harada et al., Reliability Improvement of Cu Interconnects by Additional Anneal between Cu CMP and Barrier CMP, Interconnect Technology Conference, 2003, Jun. 2-4, 2003, 92-94, Proceedings of the IEEE 2003 International.
A. H. Fischer et al., Process Optimization—The Key to Obtain Highly Reliable Cu Interconnects, Interconnect Technology Conference, 2003, Jun. 2-4, 2003, 253-255, Proceedings of the IEEE 2003 International.

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