Semiconductor memory device and manufacturing method thereof

Static information storage and retrieval – Read/write circuit – Having fuse element

Reexamination Certificate

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C365S096000, C365S230010

Reexamination Certificate

active

07548479

ABSTRACT:
A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the basis of the first internal address; and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address. The internal address supplying unit is configured to be capable of fixing a specific address bit in the first internal address. The second internal address includes: fuse independent address bits produced from address bits which is not the specific address bit in the first internal address, independently of a state of the first fuse unit, and a fuse dependent address bit having a value corresponding to the state of the first fuse unit and a vale of the specific address bit.

REFERENCES:
patent: 6202180 (2001-03-01), Nose
patent: 2008/0002511 (2008-01-01), Mou et al.
patent: 2004-265162 (2004-09-01), None

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