Sub-lithographic feature patterning using self-aligned...

Details Sub-lithographic feature patterning using self-aligned... Sub-lithographic feature patterning using self-aligned...

Filed on

2006-06-19

Date issued

2009-10-20

Examiner

Coleman, W. David (Department: 2823)

Patent Class

Semiconductor device manufacturing: process

SubClass

Coating with electrically or thermally conductive material

SubSubClass

To form ohmic contact to semiconductive material

Other Related Categories

C438S725000, C257SE21577

Type

Reexamination Certificate

Status

active

Patent number

07605081

Description

ABSTRACT:
A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w<d. Each single unit polymer block of the present invention is embedded in a polymeric matrix and can be selectively removed against the polymeric matrix to form a single opening of the diameter w in the polymeric matrix inside each of the mask openings. Sub-lithography feature patterning can then be conducted in the device structure using the single openings of diameter w.

REFERENCES:
patent: 5869364 (1999-02-01), Nakano et al.
patent: 7459793 (2008-12-01), Harada et al.
patent: 2007/0224823 (2007-09-01), Sandhu
patent: 2007/0281220 (2007-12-01), Sandhu et al.
Black, C.T. “Integration of Self Assembly for Semiconductor Microelectronics.” IEEE (2005) p. 87-91.
Nealey, Paul F. et al. “Self-Assembling Resists for Nanolithography.” IEEE (2005).
Black, C.T. “Nanometer-Scale Pattern Registration and Alignment by Directed Diblock Copolymer Self-Assembly.” IEEE (2004).

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