Semiconductor memory device comprising data path controller...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S189110, C365S194000

Reexamination Certificate

active

07623408

ABSTRACT:
A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.

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patent: 6151271 (2000-11-01), Lee
patent: 6154393 (2000-11-01), Otsuka et al.
patent: 6519189 (2003-02-01), Jung
patent: 6683638 (2004-01-01), Sato
patent: 6721232 (2004-04-01), Kashiwazaki
patent: 7020792 (2006-03-01), Hall
patent: 2001/0012233 (2001-08-01), Hirabayashi

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