Semiconductor memory device operating a self refreshing and...

Details Semiconductor memory device operating a self refreshing and... Semiconductor memory device operating a self refreshing and...

2007-12-27

2009-11-24

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S185250

Reexamination Certificate

active

07623402

ABSTRACT:
An oscillating period of an oscillator is configured to be adjustable by CODEi output from a ROM circuit, and a circuit is configured so that the oscillating period is equal to a period p times a tRAS period during self refreshing. An n-bit counter counts up based on the output of the oscillator. A programmable decoder issues a reset to the n-bit counter in a period equal to q times the oscillating period based on a count of the n-bit counter and CODEj output from the ROM circuit. Each time the programmable decoder issues the reset, an RASB signal is activated by controlling SRACT at H-level for a period equal to 1/p times the period of OSC0.

REFERENCES:
patent: 6366515 (2002-04-01), Hidaka
patent: 2002/0097626 (2002-07-01), Hidaka
patent: 05-047175 (1993-02-01), None
patent: 05-047175 (1993-02-01), None
patent: 07-078468 (1995-03-01), None
patent: 08-087883 (1996-04-01), None
patent: 08-087883 (1996-04-01), None
patent: 2001-283586 (2001-10-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device operating a self refreshing and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device operating a self refreshing and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device operating a self refreshing and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4142253