Memory integrated circuit, in particular an SRAM memory...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S390000, C257SE27098

Reexamination Certificate

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07569889

ABSTRACT:
A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

REFERENCES:
patent: 5377151 (1994-12-01), Komuro
patent: 5986914 (1999-11-01), McClure
patent: 6430076 (2002-08-01), Mueller et al.
patent: 6657880 (2003-12-01), Callahan
patent: 2001/0002882 (2001-06-01), Shimazaki et al.
patent: 2002/0036943 (2002-03-01), Fujimoto
patent: 0 593 152 (1994-04-01), None
Preliminary French Search Report, FR 05 01037, dated Oct. 26, 2005.

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